18 lines
762 B
Diff
18 lines
762 B
Diff
--- llvm-project-rocm-6.0.0/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp.bak 2024-01-30 14:27:57.942096065 +0100
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+++ llvm-project-rocm-6.0.0/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp 2024-01-30 14:29:46.408671530 +0100
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@@ -8001,12 +8001,8 @@
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IsNullOrVectorRegister = !RI.isSGPRClass(RI.getRegClassForReg(MRI, Reg));
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}
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- uint16_t Opc = MI.getOpcode();
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- // FIXME: Copies inserted in the block prolog for live-range split should also
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- // be included.
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- return IsNullOrVectorRegister &&
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- (isSpillOpcode(Opc) || (!MI.isTerminator() && !MI.isCopy() &&
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- MI.modifiesRegister(AMDGPU::EXEC, &RI)));
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+ return !MI.isTerminator() && !MI.isCopy() &&
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+ MI.modifiesRegister(AMDGPU::EXEC, &RI);
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}
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MachineInstrBuilder
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