--- llvm-project-rocm-6.0.0/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp.bak	2024-01-30 14:27:57.942096065 +0100
+++ llvm-project-rocm-6.0.0/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp	2024-01-30 14:29:46.408671530 +0100
@@ -8001,12 +8001,8 @@
     IsNullOrVectorRegister = !RI.isSGPRClass(RI.getRegClassForReg(MRI, Reg));
   }
 
-  uint16_t Opc = MI.getOpcode();
-  // FIXME: Copies inserted in the block prolog for live-range split should also
-  // be included.
-  return IsNullOrVectorRegister &&
-         (isSpillOpcode(Opc) || (!MI.isTerminator() && !MI.isCopy() &&
-                                 MI.modifiesRegister(AMDGPU::EXEC, &RI)));
+  return !MI.isTerminator() && !MI.isCopy() &&
+         MI.modifiesRegister(AMDGPU::EXEC, &RI);
 }
 
 MachineInstrBuilder
